The present invention relates to semiconductor memory devices and, more particularly, to a semiconductor memory device having a redundancy unit for data line compensation.
Generally, conventional semiconductor memory devices, such as a synchronous dynamic random access memory (SDRAM), include a redundancy unit that uses a shift redundancy system. FIG. 1 is a circuit diagram of a conventional redundancy unit 100 that uses a shift redundancy system.
As shown in FIG. 1, the redundancy unit 100 comprises sixteen data bus lines DB0 to DB15, and a single redundancy data bus line DBs provided for the data bus lines DB0 to DB15. The first to sixteenth data bus lines DB0 to DB15 are connected to first to sixteenth input/output data lines DL0 to DL15 through related first to sixteenth shift switches SW0 to SW15, respectively. Sense buffers SB0 to SB15 and write amplifiers WA0 to WA15 are connected between the first to sixteenth shift switches SW0 to SW15 and the first to sixteenth input/output data lines DL0 to DL15, respectively.
The first to fifteenth shift switches SW0 to SW14 switch the connection of the first to fifteenth input/output data lines DL0 to DL14 between the first to fifteenth data bus lines DB0 to DB14 and the second to sixteenth data bus lines DL1 to DB15, each of which is one bit higher than each of the first to fifteenth data bus lines DB0 to DB14. The sixteenth shift switch SW15 switches the connection of the sixteenth input/output data line DL15 between the sixteenth data bus line DB15 and the redundancy data bus line DBs.
For example, when a defect occurs at the fourteenth data bus line DB13, the shift redundancy operation is performed using the shift switches SW13, SW14 and SW15. More specifically, the connection of the fourteenth input/output data line DL13 is switched to the fifteenth data bus line DB14, the connection of the fifteenth input/output data line DL14 is switched to the sixteenth data bus line DB15, and the connection of the sixteenth input/output data line DL15 is switched to the redundancy data bus line DBs.
That is, in the shift redundancy system, the connection of both of a defective one and the rest of the data bus lines DB0 to DB15 is switched, using the related shift switches SW0 to SW15, to the normal upper rank data bus lines DB0 to DB15 and to the redundancy data bus line DBs, sequentially. As a result, a semiconductor memory device that functions normally is implemented.
By the way, in the conventional shift redundancy system, the shift switches SW0 to SW15 are closer to bit lines BL than the sense buffers SB0 to SB15 and the write amplifiers WA0 to WA15, respectively.
During a read operation, data read from memory cells (not shown) has a very small amplitude until it reaches the sense buffers SB0 to SB15 via sense amplifiers SA. When the sense buffers SB0 to SB15 amplify the data whose amplitude is very small, the ON resistance and parasitic capacitance of the shift switches SW0 to SW15 are added to the load on the data bus lines DB0 to DB15 and DBs, and thus the bus logic of the sense buffers SB0 to SB15 is hard to invert. The same problem is encountered by the write amplifiers WA0 to WA15 during a write operation.
In order to make the logic inversion easier, there is a technique in which the size of the shift switches SW0 to SW15 is increased so that the effects of the ON resistance and parasitic capacitance of the shift switches SW0 to SW15 is reduced. However, larger shift switches SW0 to SW15 bring about another problem in that the circuit area is increased and thus it becomes difficult to lay out the switches SW0 to SW15 within a pitch of the data bus. Further, another problem is that the power consumption of the semiconductor memory device increases.